In the last decade, electroplating has emerged as a key technology in the fabrication of the next generation of electronic devices. In this respect, the next generation of electronic devices is required to be lighter, have a larger processing capacity and to possess a higher degree of functionality than present devices. In order to achieve this, electronic devices have begun to utilize a technique known as 3-D wafer stacking in which several individual devices (or wafers and metal layers) are stacked together, and vertically interconnected to each other by conducting posts that are formed within through-hole vias of said devices. The conducting posts are typically electroplated into the through-hole vias.
Vertical interconnection between individual devices is preferred as the vertical axis offers the shortest possible electrical interconnect length. Accordingly, vertical interconnection results in lower parasitic losses, RC delay and thus, gives rise to faster response times.
An example of a material favored for forming said vertical interconnects is Copper (Cu), due to its high electrical conductivity and high electromigration resistance. Copper is typically deposited by an electroplating process. This process allows for the deposition of a layer several hundred microns thick. An advantage of electrodeposition, as compared to other physical deposition processes like sputtering, e-beam evaporation and chemical vapor deposition (CVD), is that the electroplating process is cheaper, faster and requires a lower temperature, comparatively.
Although electroplating of metals such as copper or nickel is a well established process and its principles are generally well known, complete void free filling of through-holes is still a challenging task. U.S. Pat. No. 6,340,633 attempts to address the problem by utilizing a method of electroplating copper in a via in a thin layer wherein a reverse pulse current density is supplied and ramped, i.e. the forward pulse current density increases over each successive pulse while the reverse pulse current density is kept constant. As the forward current density increases, the grain size of the copper deposited in the via also increases. Accordingly, the method disclosed here intends for an initial low forward pulse current density to be applied, followed by increasing forward pulse current densities in order that copper of a small grain size fills the bottom of the via initially, while copper of a larger grain size fills the higher portions of said via, as the interconnect is built up.
For high aspect ratio through-holes, the inventors in this patent application have found that the incomplete filling of a through-hole via, and void formation therein, lies firstly, in the high aspect ratio of the via itself, and secondly, due to the insufficient wetting of the side walls of the through-hole vias with copper electrolyte. For the first reason, high aspect ratio (where value of the aspect ratio is greater than 10) vias undergoing electroplating have an uneven local current density that results in an uneven distribution of copper being deposited. Typically, the current density is higher at each corner point inside the through-holes and lower along the vias. In high aspect ratio through-hole vias, the current density does not remain uniform along the depth during the electroplating process. The current density at the entry and exit of said via, is typically higher than that at the center. Due to higher current density at the corners, the copper deposition rate at the corners is greater than at the center of the vias. As a result of this uneven deposition of copper, the entrance of the vias eventually becomes blocked at the top and the bottom thereby forming a void in the center.
As for the second reason, in high aspect ratio through-holes, the electrolyte does not wet the via sidewall surface completely and in some cases, said electrolyte even does not reach the bottom of the via. This problem is further compounded due to the present use of deep reactive ion etching (DRIE) to etch through-holes in silicon substrates. During the passivation step of the DRIE process, a thin layer of polymer is deposited on the side walls to protect it from lateral etching. This polymer (Poly-tetra-fluoro compound) is a hydrophobic material, which prevents the wetting of the via surface with copper electrolyte. Due to insufficient interaction between the copper electrolyte and some local points on the via surface, again, the current density distribution, as mentioned above, varies, which results in non-uniform copper deposition along the through-via surface.
As such, there is a need for a method of electro-depositing conductive material in through-hole vias having a high aspect ratio that results in the formation of void free interconnects, is compatible with existing fabrication technology and is cost-effective as well.